1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatuses, and computer program products for accessing a logic device through a serial interface.
2. Description of Related Art
Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One of the areas that has seen considerable advancement is the use of serial interfaces, as it decreases the number of signals used, thus allowing for a smaller package. This has been facilitated by the use of programmable logic devices or ‘PLDs.’ PLDs are used for glue logic, power control, translation of interfaces such as I2C to SPI, debugging interfaces, isolation of failed boards, a variety of boot functions and power-on-self-test or ‘POST’ and for many other system-level computer operation functions known to those of skill in the art. The exact use of any particular PLD changes from one computer design to another—as well as within any particular computer design from time to time. This is a particular strength of PLDs—that system designers can change their functions even within the same system over time as needs evolve or designs improve.
One function that PLDs perform is quick memory storage. For example, serial presence data may be stored in a PLD, such as a field programmable gate array (FPGA), for access by a service processor prior to the system boot. In this example, to retrieve the data from the FPGA, the service processor may transmit to the FPGA through a serial interface, a read transaction that includes an address within the FPGA. In a FPGA addressed in a linear address mode, each block of memory is assigned a linear address. The number of linear addresses available to a FPGA is limited by the size of a linear address. Increasing the size of each linear address increases the overhead in processing data access requests. As a consequence of operating in the linear address mode, the capabilities of PLDs are limited.